The fabrication of silicon based solar cells requires a number of specialized processes to occur in a specific order. First, long “sausage-shaped” single crystal masses called ingots, or multi-crystalline blocks are produced, from which thin slices of silicon are cut transversely with “wire saws” to form rough solar cell wafers. Rough wafers are then processed to form smooth wafers in the 150 to 330 micrometer range of thickness. Because of the scarcity of suitable silicon, the current trend is towards making the wafers thinner, typically 180 micrometers thick.
Finished raw wafers are then processed into functioning solar cells, capable of generating electricity by the photovoltaic effect. Wafer processing starts with various cleaning and etching operations, ending in a process called diffusion doping which creates a semi-conducting “p-n”, junction diode, the layer that emits electrons upon exposure to sunlight (the normal photon source). These electrons are collected by a fine web of screen printed metal contacts that are sintered into the surface of the cell, as described in more detail below.
To enhance the ability to form low resistance screen-printed metal contacts to the underlying silicon p-n junction emitter layer, additional amounts of phosphorus are deposited onto the front surface of the wafer. The phosphorous is driven into the wafer via a high temperature diffusion process lasting up to 30 minutes. After diffusion and various cleaning and etching processes to remove unwanted semi-conductor junctions from the sides of the wafers, the wafers are coated with an anti-reflective coating, typically silicon nitride (SiN3), generally by plasma-enhanced chemical vapor deposition (PECVD deposited to a thickness of approximately ¼ the wavelength of light of 0.6 microns. After ARC application, the cells exhibit a deep blue surface color. The ARC minimizes the reflection of incident photons having wavelengths around 0.6 microns.
During ARC SiNx coating PECVD process, hydrogen dissociates and diffuses very rapidly into the silicon wafer. The hydrogen has a serendipitous effect of repairing bulk defects, especially in multi-crystalline material. However, during subsequent IR firing, elevated temperatures (above 400° C.) will cause the hydrogen to diffuse back out of the wafer. Thus, short firing times are necessary to prevent this hydrogen from ‘out-gassing’ from the wafer. It is best that the hydrogen is captured and retained within the bulk material (especially in the case of multi-crystalline material).
The back of the solar cell is covered with an Al paste coating which is “fired” in an IR furnace to alloy it with the doped silicon, thereby forming a “back surface field”. Alternately, the back surface aluminum paste is dried, then the wafer is flipped-over for screen-printing the front surface with silver paste in electrical contact patterns which are also dried. The two materials, back surface aluminum and front surface silver contact pastes are then co-fired in a single firing step which saves one processing step. The back surface aluminum paste melts (“alloys”) into a continuous coating, while the front surface paste is sintered at high speed and at high temperature to form smooth, low ohmic resistance conductors on the front surface of the solar cell.
The instant invention is directed to co-firing alloying/sintering processes and IR furnaces for such co-firing or other industrial processes. Currently available IR conveyor furnaces have an elongated, tunnel-like horizontally-oriented heating chamber, divided along its length into a number of zones. Each zone is insulated from the outside environment. Typically, the first zone, just inside the entrance is supplied with a larger number of infra-red (IR) lamps, then the next 2 or 3 zones to rapidly increase the temperature of the incoming silicon wafers to approximately 425° C. to 450° C. This temperature is held for the next few zones to stabilize the wafers' temperature and insure complete burn-out of all organic components of the pastes, to minimize all carbon content within the contacts so as to not increase contact resistance.
Fast firing generally gives optimum results because the impurities do not have time to diffuse into the emitter. A high rate of firing is critical as the activation energy for the impurities to diffuse into the doped Si emitter region is generally lower than that for sintering the silver particles. To achieve this high firing rate, the wafers enter a high IR-intensity “spike” zone where the wafers' temperature is quickly raised into the range of 700-950° C., and then cooled, by a variety of means, until the wafers exit the furnace. The wafers are not held at the peak temperature. Rather, the peak width should be minimal, that is, the dwell time short, while the ascending and descending rate slopes should be steep.
However, in the current state of the IR furnace art these desiderata are not met. Rather, the high intensity spike zone is simply a copy of the first zone wherein IR lamps are arrayed transverse to the longitudinal axis of the furnace zones, i.e., across the full width of the wafer transport belt, both above and below the belt and its support system. As a result, the current art suffers from highly inefficient use of the IR lamps that heat the wafers in the various processing zones, and a shallow excess dwell time characterized by a broad peak and shallow rate temperature curves (slopes) in the spike zone. Currently available furnaces are able to generate in the range of from about 80° C. to about 100° C./second rate of temperature rise in the spike zone. Since the peak temperature must approach 1000° C., the currently available rate of rise at the constant conveyor transport rate requires the spike zone to be physically long since the belt moves at a constant speed. The dwell peak of current processes (dwell time at peak temperature) is also too broad; that is, too long.
The shallow curve/broad peak characteristic process limitation of currently available furnaces has deleterious effects on the metal contacts of the top surface which significantly limits cell efficiency. It is important to accomplish the firing sequence quickly for several reasons. First, the frit glass must not flow too much, otherwise the screen-printed contact lines will flow, widening and thereby reducing the effective collection area by blocking more of the cell surface from incident solar radiation. Secondly, the glass frit should not mix with the silver particles to any great extent since this will increase series resistance of the contacts. Finally, all of this material must etch through the SiNx anti-reflective (ARC) coating (about 0.15 micrometers in thickness or ¼ of the 0.6 micrometer target wavelength for reflection minimization), but must not continue to drive through the “shallow”, doped Si emitter layer, previously formed by the diffusion of phosphorus onto the top surface of the p-type silicon. Emitters are generally 0.1 to 0.5 micrometers in thickness, but shallow emitters are generally in the 0.1 to 0.2 micrometer range.
Thus, to control the etch depth, the sinter must be quenched both quickly and thoroughly. Quenching, that is, preventing diffusion of the silver particles into the silicon below the emitter (forming crystallites) after etching the AR coating and creating good adhesion of the glass to the silicon substrate, must be accomplished by rapid cooling. This is critical. If the silver drives too deep into the doped Si emitter layer, the junction is shorted. The result is that the cell looses efficiency due to a short circuit path for the electrons produced. This is also known as a low shunt resistance property of the cell.
But in contradiction, it is also vitally necessary to slow down rapidity of cooling in order to anneal the glass phase to improve adhesion. Taken together, the cooling curve looks like this: rapid cooling from the peak firing temperature to about 700° C., then slow cooling for annealing purposes, then rapid cooling to allow the wafer to exit the furnace at a temperature low enough to be handled by robotics equipment that must have rubberized suction cups to lift the wafers off the moving conveyor without marring the surface.
Since there are dimensional and IR lamp cost constraints, increasing lamp density in the spike zone is not generally a feasible solution. In addition, the peak temperature is held only for a few seconds at most in the spike zone and the descending thermal profile needs to be sharp. Increasing lamp density can be significantly counter-productive, in that the increased density easily results in a more gradual slope due to the reflection off the product and the internal surfaces of the spike zone.
Likewise, increasing the power to the lamps is not currently feasible because higher output can result in overheating of the lamp elements, particularly the external quartz tubes. When the thermocouples detect temperatures approaching 900° C., they automatically cut back power to the lamps. This results in lower power density, changes in the spectral output of the IR lamp emissions (hence a lower energy output), and results in the need to slow down the conveyor belt speed, thus slowing processing. In turn, this results in a ripple effect into the other zones. Since the belt is continuous, slowing in one zone slows the belt in all zones, so that adjustments must be made in all zones to compensate. In turn, slowing upstream or downstream zones affects the firing zone. Overheating of lamps, e.g., due to thermocouple delay or failure, can cause the lamps to deform, sag and eventually fail. This deformation also affects uniformity of IR output delivered to the product.
There are additional problems presented by the current state of the art furnaces which are solved by the present invention. Factory floor space is at a premium and furnace equipment is expensive so that wafer production facilities are typically single building configurations housing many furnaces arrayed in parallel orientations. Adding a new furnace requires free floor space. An alternative has been to install wider furnaces having conveyor belts on which two or more wafers may be placed side by side. Thus, a furnace with an 18″ wide belt can process wafers 2-wide, that is, a double-line or “2-up” furnace, in substantially less floor space than two single line furnaces employing 10″ wide belts.
However, the disadvantage is that one size does not fit all. That is, both lines are subject to the same process control parameters, which may result in lower yield, or power output for individual cells, being adjusted for the average of the two lines. Further, uniformity of temperature, and lamellar atmosphere control is adversely affected by increased furnace width. In addition, as furnaces get wider, there is greater occurrence of IR lamp sag failure, as they are unsupported across the furnace at the hottest point.
Finally, different batches of wafers may need to be processed at very different thermal profiles, or across-the-belt thermal variations may result in production wastage in 2-up, wide belt furnaces. With single, full-width lamps, control of each line is not possible in conventional furnaces.
Accordingly, there is an unmet need in the IR furnace and IR firing process art to significantly improve net effective heating rate of conventional lamps, to provide better control and thermal profiles in each wafer lane in the spike zone, to permit improved control of furnace temperature and atmosphere conditions, to improve quenching and annealing profiles, to improve the uniformity of heat in furnace zones, and to improve throughput of such furnaces, while accomplishing these goals on the same or net reduced furnace foot-print. There is an unmet need to provide individual wafer line thermal profile control throughout the zones in double-wide, 2-up furnaces without increasing the furnace width.